Course Content
Introduction and Recap (1 lecture): RISC Instruction Set Architecture, Instruction Semantics and single cycle execution, pipelined execution (basic five-stage pipeline), Memory hierarchy (size and typical access latency of multiple levels of caches and main memory), microarchitecture of a cache (control bits, tag array and data array, block size, associativity)
Instruction Level Parallelism (14 lectures, 14 lab hours) Introduction to superscalar architectures, Out-of-Order processing - branch predictors, predicting indirect jumps and returns, micro-op cache, instruction rename, instruction dispatch, dynamic scheduling (wakeup and select), load store queue, instruction commit (precise and imprecise exceptions), multi-threading (coarse-grained, fine-grained and simultaneous).
Thread Level Parallelism (14 lectures, 10 lab hours) Multi-core architecture, cache coherence - challenge and solutions (shared and directory-based), memory consistency
Data Level Parallelism (5 lectures) Vector Architecture and SIMD, Graphics Processing Unit (GPUs), Exploiting Loop-level parallelism
Recent Advances and Enhancements (8 lectures) Instruction and Data prefetching, Transactional Memories, Processing near/in memory, On-Chip Networks, Domain-specific Accelerators
NOTE: The lab exercises could include performance profiling using tools such as Linux Perf, as well as Simulation studies (including feature implementations) on cycle-accurate architectural simulators such as GEM5 and Tejas.
Learning Outcomes
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Understand the microarchitecture of modern processors well which will help in workload profiling, performance optimization of programs, improve the performance of code generated by compilers, etc.
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Get acquainted with tools and techniques used for performance modeling and feature exploration of next generation of general purpose processors
Text Books
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Computer Architecture: A Quantitative Approach, David Patterson and John L. Hennesy, Elsevier, Sixth edition. 2017. ISBN: 978-0-12-811905-1
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Advanced Computer Architecture, Smruti Ranjan Sarangi, 2021. ISBN: 978-93-90727-49-0
Reference Books
- Lectures by Onur Mutlu (available online, Youtube)
- Research Articles published in reputed conferences and journals such as ISCA, MICRO, HPCA, TACO, and CSUR.
Past Offerings
Course Metadata
| Item | Details |
|---|---|
| Course Title | Architecture of High Performance Processors |
| Course Code | CS5655 |
| Course Credits | 3-0-2-4 |
| Course Category | PME |
| Proposing Faculty | Sandeep Chandran |
| Approved on | Senate of IIT Palakkad |
| Course status | New |