Prerequisites: Digital System Design, Verilog

Syllabus

  1. Introduction to Functional Verification–Concepts, Challenges, Simulators, Verification Approaches: black box, white box and grey box verification (4 lectures)
  2. Verification Methodologies: Testing strategy, Directed and random Testing, Test Cases Vs Test Benches, Verification Components (Drivers, Checkers, Monitors, Scoreboards etc) (8 lectures)
  3. SystemVerilog Paradigm: Limitations of Verilog for verification, Hardware Verification Languages, Object oriented programming for ASIC Verification, PLI and DPI Basics (7 lectures)
  4. Measuring the quality of verification: Code coverage, Functional coverage, Coverage Driven Verification, Assertion based verification, Coverage Analysis. (7 lectures)
  5. SystemVerilog Universal Verification Methodology (UVM) components and practices (6 lectures)
  6. Architecting Test benches: Building actual test benches based on SystemVerilog from grounds up (8 lectures)

Course Objectives

The objective of this course is to teach student everything about pre-silicon functional verification of VLSI RTL designs. Emphasis of the course is on frontend design & verification methodologies and on their practical applications. The course contents have been designed keeping in view the emerging trends in needs for skilled manpower in ASIC/SOC industry.

Learning Outcomes

  1. Thorough working knowledge in writing test benches 
  2. Proficiency in industry standards and methodologies for functional verification of ASIC/SOC designs

Text Books

  1. ASIC/SoC Functional Design Verification - Ashok B Mehta
  2. SystemVerilog for Verification – Chris Spear
  3. SystemVerilog Assertions Handbook: – for Formal and Dynamic Verification – By Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari

References

  1. Writing Testbenches using SystemVerilog – Janick Bergeron
  2. Principles of Functional Verification – Andreas Meyer

Past Offerings

  • Offered in Jan-May, 2022 by Kiran (Intel), Vivek Chadurvedi