Prerequisite: Basic Data Structures, VHDL/Verilog

Course Contents

VLSI Design Flow: Hardware modelling principles and modern Hardware description Languages - Bluespec, High Level Design Representation (3 lectures)

High Level (or Behavioral) Synthesis: Scheduling, Allocation, and Binding Problem; Algorithms for Scheduling, Binding and Allocation (12 lectures)

Register Transfer Level Synthesis: Re-timing and Finite State Machine Encoding techniques (3 lectures)

Logic Synthesis: Two level Boolean Logic Synthesis, and Heuristic based Minimization, Multi-level Implementations (12 lectures)

Layout Synthesis: Introduction to Placement, Technology Mapping, Routing and Timing Analysis (12 lectures)

Learning Objective

This course aims to give an overview of the VLSI Design flow, introduce the challenges in synthesizing digital circuits, and the various algorithms and techniques that address these challenges.

Learning Outcome

Upon successful completion of the course, students would be able to:

  • Recall the steps in a typical VLSI Design flow
  • Understand the requirements from a High-level Hardware Description Language (HDL)
  • Appreciate the challenges involved in synthesizing digital circuits from behavioral specifications of the circuit
  • Apply algorithmic techniques to solve these challenges

Text Books

  1. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill Education; 1st edition (1 July 2017), ISBN: 978-0070582781

Reference Books

  1. Sabih H. Gerez, Algorithms for VLSI Design Automation, Wiley (1 January 2006), ISBN: 978-9758729708
  2. Wayne Hendrix Wolf, FPGA-Based System Design, Pearson Education; 1st edition (1 January 2005), ISBN: 978-8131724651

Metadata

Proposing Faculty: Dr. Sandeep Chandran Department: Computer Science and Engineering Programme: B.Tech Proposing date: 25-11-2020 Approved date: Proposal type: Offerings:

Past Offerings

  • Offered in Jan-May, 2021 by Sandeep