Introduction to EDA Tools: Fundamentals of EDA, ASIC design flow using EDA tools with case studies, FPGA design flow
Architecture design: RTL Coding, functional verification through dynamic simulation, Synthesis and Timing: Static timing analysis, gate level simulations,
Formal Verification: Assertion based formal verification, Model Checking using formal toolchain
Physical Design: Floor planning, placement and routing, design for testability, scan based methodology, clock tree synthesis, parasitic extraction and back annotation, physical verification and GDSII generation
System Integration: Design a system - accelerator, memory, processor, interconnect, and integrate and test it on the FPGA/ASIC. (Introduction to both ASIC and FPGA flow, and complete FPGA flow)
Past Offerings
- Offered in Jan-May, 2025 by Sabarimalai Manikantan
- Offered in Jan-May, 2021 by Satyajit
Course Metadata
| Item | Details |
|---|---|
| Course Title | SoC Design Lab |
| Course Code | CS5102 |
| Course Credits | 1-0-3-3 |
| Course Category | PMP |
| Approved on | Senate of IIT Palakkad |